Testability Concepts for Digital ICs The Macro Test Approach LN

Description: About this productProduct InformationPreface Testing Integrated Circuits for manufacturing defects includes four basic disciplines. First of all an understanding of the origin and behaviour of defects. Secondly, knowledge of IC design and IC design styles. Thirdly, knowledge of how to create a test program for an IC which is targeted on detecting these defects, and finally, understanding of the hardware, Automatic Test Equipment, to run the test on. All four items have to be treated, managed, and to a great extent integrated before the term 'IC quality' gets a certain meaning and a test a certain measurable value. The contents of this book reflects our activities on testability concepts for complex digital ICs as performed at Philips Research Laboratories in Eindhoven, The Netherlands. Based on the statements above, we have worked along a long- term plan, which was based on four pillars. 1. The definition of a test methodology suitable for 'future' IC design styles, 2. capable of handling improved defect models, 3. supported by software tools, and 4. providing an easy link to Automatic Test Equipment. The reasoning we have followed was continuously focused on IC qUality. Quality expressed in terms of the ability of delivering a customer a device with no residual manufacturing defects. Bad devices should not escape a test. The basis of IC quality is a thorough understanding of defects and defect models.Product IdentifiersPublisherSpringerISBN-100792396588ISBN-139780792396581eBay Product ID (ePID)746103Product Key FeaturesAuthorF. P. Beenker, A. P. Thijssen, R. G. BennettsPublication NameTestability concepts for Digital Ics : the Macro Test ApproachFormatHardcoverLanguageEnglishSeriesFrontiers in Electronic Testing Ser.Publication Year1995TypeTextbookNumber of PagesIX, 212 PagesDimensionsItem Length9.6inItem Width6.7inItem Weight38.8 OzAdditional Product FeaturesSeries Volume Number3Number of Volumes1 Vol.Lc Classification NumberTk7867-7867.5Table of ContentPreface. 1. Introduction. 2. Defect-Oriented Testing. 3. Macro Test: A Framework for Testable IC Design. 4. Examples of Leaf-Macro Test Techniques. 5. Scan Chain Routing with Minimal Test Application Time. 6. Test Control Block Concepts. 7. Exploiting Parallelism in Leaf-Macro Access. 8. Timing Aspects of CMOS VLSI Circuits. List of Symbols and Abbreviations. References. Index.Copyright Date1995Target AudienceScholarly & ProfessionalTopicIndustries / Retailing, Electronics / Circuits / Integrated, Electronics / Circuits / General, ElectricalLccn95-040166Dewey Decimal621.3815/48Dewey Edition20IllustratedYesGenreTechnology & Engineering, Business & Economics

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