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Digital Logic Design Using Verilog - 9788132227892

Description: Digital Logic Design Using Verilog Please note: this item is printed on demand and will take extra time before it can be dispatched to you (up to 20 working days). Coding and RTL Synthesis Author(s): Vaibbhav Taraate Format: Hardback Publisher: Springer, India, Private Ltd, India Imprint: Springer, India, Private Ltd ISBN-13: 9788132227892, 978-8132227892 Synopsis This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.

Price: 133.56 GBP

Location: Aldershot

End Time: 2024-11-26T09:12:28.000Z

Shipping Cost: 40.06 GBP

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Digital Logic Design Using Verilog - 9788132227892

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Book Title: Digital Logic Design Using Verilog

Item Height: 235 mm

Item Width: 155 mm

Author: Vaibbhav Taraate

Publication Name: Digital Logic Design Using Verilog: Coding and Rtl Synthesis

Format: Hardcover

Language: English

Publisher: Springer, India, Private LTD

Subject: Engineering & Technology, Computer Science, Physics

Publication Year: 2016

Type: Textbook

Item Weight: 8602 g

Number of Pages: 416 Pages

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